搜索资源列表
KD-CPU
- 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
CPU_data_path_design_is_very_simple
- 居于硬件描述语言的简单CPU设计，能够实现比较简单的数据传送处理功能，虽然功能简单，但只要搞懂了其中原理，对于大的系统就能够有依葫芦画瓢的强大效果。-Living in a simple CPU hardware descr iption language design, to achieve relatively simple data transfer processing functions, although the functionality is simple, but as lon
cpu
- 16位的CPU的VHDL程序~~还有附加的生成波形，可以应用于课程设计中-16-bit CPU, VHDL ~ ~ There are additional procedures for generating waveforms, can be applied to curriculum design
cpu
- 8位CISC模型计算机设计，包括加减法存储输出的运算-8-bit CISC model of computer design, including the addition and subtraction operations stored output
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
cpu
- 组成原理实验~简单cpu的设计~基于EDA环境下的-Composition Theory Experiment Design ~ ~ Simple cpu EDA environment based on
CPU-design
- 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
CPU-card-reference-design-operation
- CPU卡又被称为智能卡，由于其具有很高的数据处理和计算能力以及较大的存储器容量，因此具有较强的应用灵活性和适应性。 本文主要讲述CPU卡操作参考设计！仅供参考-CPU card reference design operation
CPU--design
- 该文档很好的介绍了8位cpu的设计，代码非常详细，很好的参考资料-The document describes a good design of 8-bit cpu, code is very detailed, good reference
CPU-IC
- CPU卡一些资料，CPU IC卡系统通讯协议及底层程序的设计，CPU卡详解-CPU card with some information, CPU IC card system communication protocol and the underlying process of design, CPU card Detailed
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
CPU-source-code
- CPU设计代码，包括单周期CPU，多周期CPU，流水线CPU及相关ALU组件。-CPU design code, including single-cycle CPU, multi-cycle CPU, ALU pipeline CPU and related components.
Digital-Design-Through-Verilog
- cpu design an intutive approach raja sekhar 08-12
cpu-and-ram
- 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
16-bit-CPU
- 单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书-Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
CPU
- CPU设计时间报告，VHDL含有详细代码，下载到实验台后能用-Can be used after the the CPU design time report, VHDL contains detailed code downloaded to the bench